A 27 GHz double polysilicon bipolar technology on bonded SOI with embedded 58 mu m/sup 2/ CMOS memory cells for ECL-CMOS SRAM applications

Author

Hiramoto, T. ; Tamba, N. ; Yoshida, M. ; Hashimoto, T. ; Fujiwara, T. ; Watanabe, K. ; Odaka, M. ; Usami, M. ; Ikeda, T.

Author_Institution

Device Dev. Center, Hitachi Ltd., Tokyo, Japan

fYear

1992

fDate

13-16 Dec. 1992

Firstpage

39

Lastpage

42

Abstract

A double polysilicon bipolar technology with high-speed, high-packing density, low power consumption, and high alpha -particle immunity has been newly developed. Bonded SOI substrates are used to improve the alpha -particle immunity, and scaled CMOS memory cells are introduced to reduce the power consumption and to increase the packing density. The cut-off frequency of the bipolar transistors is as high as 27 GHz and the area of the CMOS memory cell is 58 mu m/sup 2/. This technology is promising for application to ultra high-speed, high-density LSIs with ECL-CMOS scheme.<>

Keywords

BiCMOS integrated circuits; SRAM chips; emitter-coupled logic; large scale integration; radiation hardening (electronics); semiconductor-insulator boundaries; 27 GHz; ECL-CMOS SRAM applications; alpha -particle immunity; bonded SOI; bonded SOI substrates; cut-off frequency; double polysilicon bipolar technology; embedded CMOS memory cells; high-density LSIs; packing density; power consumption; scaled CMOS memory cells; BiCMOS integrated circuits; Emitter coupled logic; Large-scale integration; Radiation hardening; SRAM chips; Semiconductor-insulator interfaces;

fLanguage

English

Publisher

ieee

Conference_Titel

Electron Devices Meeting, 1992. IEDM '92. Technical Digest., International

Conference_Location

San Francisco, CA, USA

ISSN

0163-1918

Print_ISBN

0-7803-0817-4

Type

conf

DOI

10.1109/IEDM.1992.307304

Filename

307304