DocumentCode :
1951332
Title :
Swathbuckler wide area SAR processing front end
Author :
Rouse, Shane ; Bosworth, Duncan ; Jackson, Alex
Author_Institution :
Sensors & Countermeasures Dept., Defence Sci. & Technol. Lab., Malvern, United Kingdom
fYear :
2006
fDate :
24-27 April 2006
Abstract :
The Swathbuckler international collaboration task between government laboratories of US, Canada, UK and Australia has jointly implemented an affordable, experimental, real-time, wide-swath SAR imaging radar system. This paper is one of a coordinated collection of papers submitted by the collaboration partners. It describes the radar processing front-end component of Swathbuckler, responsible for the intelligent interface between SAR radar and the high-performance computing cluster. The unique requirements of this program, namely the real-time processing of SAR swaths encompassing 250,000 range samples, dictated a novel reconfigurable FPGA architecture for this interface. The associated firmware performs high-speed digitization, digital down-conversion and distribution to each of the nodes in the computing cluster. The design has evolved from early attempts to develop a custom prototype through to an integrated solution using commercially available hardware. The interface has successfully flown in Swathbuckler flights supporting wide-swath, high resolution SAR processing at a sustained 500 Hz pulse repetition frequency. The work has demonstrated that it is possible, with currently available and technology, to provide an affordable, compact means of managing unprecedented SAR swath sizes in an airborne platform.
Keywords :
airborne radar; field programmable gate arrays; firmware; image resolution; radar computing; radar imaging; radar resolution; real-time systems; reconfigurable architectures; synthetic aperture radar; 500 Hz; Australia; Canada; Swathbuckler international collaboration task; UK; US; airborne platform; digital down-conversion; field programmable gate array; firmware; front-end component; high-performance computing cluster; high-speed digitization; intelligent interface; pulse repetition frequency; real-time processing; reconfigurable FPGA architecture; resolution; synthetic aperture radar; wide-swath SAR imaging radar system; Australia; Computer architecture; Computer interfaces; Field programmable gate arrays; International collaboration; Radar imaging; Radar polarimetry; Real time systems; Synthetic aperture radar; US Government;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Radar, 2006 IEEE Conference on
Print_ISBN :
0-7803-9496-8
Type :
conf
DOI :
10.1109/RADAR.2006.1631873
Filename :
1631873
Link To Document :
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