DocumentCode :
1951358
Title :
Source/drain elevation process using implantation enhanced selective etching
Author :
Huda, M.O. ; Sakamoto, K. ; Tanoue, H.
Author_Institution :
Nanoelectron. Res. Inst., Nat. Inst. of Adv. Ind. Sci. & Technol., Tsukuba, Japan
fYear :
2002
fDate :
2-3 Dec. 2002
Firstpage :
51
Lastpage :
54
Abstract :
A technique for formation of elevated source/drain structure has been demonstrated. 100 nm thick epitaxial silicon/polysilicon layer was formed on patterned Si/SiO/sub 2/ structure by chemical vapor deposition (CVD) at 700/spl deg/C. Structural damage was selectively introduced in polysilicon layer by a low dose Argon implantation at 140 keV. Crystal damage in epitaxial silicon layer was kept minimum by aligning the implantation in vertical <100> channeling direction. A short duration post-anneal at 420/spl deg/C was used for structural recovery of the silicon layer. Polysilicon layer was then selectively removed by wet etching. With careful selection of implantation dose and energy, we were able to avoid the commonly observed faceting effect of elevated silicon layer near pattern edges.
Keywords :
CVD coatings; MOSFET; elemental semiconductors; etching; ion implantation; semiconductor epitaxial layers; silicon; silicon compounds; 100 nm; 140 keV; 420 degC; 700 degC; Si-SiO/sub 2/; argon implantation; chemical vapor deposition; drain elevation process; epitaxial silicon-polysilicon layer; implantation enhanced selective etching; patterned Si/SiO/sub 2/ structure; source elevation process; structural recovery; Annealing; Argon; Chemical vapor deposition; Electrostatic discharge; Epitaxial growth; Insulation; Silicides; Silicon on insulator technology; Surface morphology; Wet etching;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Junction Technology, 2002. IWJT. Extended Abstracts of the Third International Workshop on
Conference_Location :
Tokyo, Japan
Print_ISBN :
4-89114-028-3
Type :
conf
DOI :
10.1109/IWJT.2002.1225201
Filename :
1225201
Link To Document :
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