Employment of Reduced Precision Redundancy for Fault Tolerant FPGA Applications

This research explores the employment of Reduced Precision Redundancy (RPR) as a power saving alternative to traditional Triple Modular Redundancy (TMR). This paper focuses on the details of RPR implementation and the effect of RPR fault tolerance on the performance of spacecraft systems. RPR-protected system performance is evaluated using a signal-to-noise ratio analogy developed with Matlab and Simulink computational tools. This research demonstrates that RPR is an effective fault tolerance approach for arithmetic operations. Experimental results show that the benefit of RPR increases with the complexity of the operation to which it is applied. System performance simulations demonstrate that RPR provides very good recovery from errors caused by SEE in spacecraft systems.