A normalized intrinsic delay model of static CMOS complex gates for deep submicron technologies

Author

Xue, Jingyue ; Al-Khalili, Dhamin ; Rozon, Côrne N.

Author_Institution

Dept. of Electr. & Comput. Eng., R. Mil. Coll. of Canada, Kingston, Ont., Canada

fYear

2004

fDate

20-23 June 2004

Firstpage

17

Lastpage

20

Abstract

In this paper, we present a delay model that can estimate the normalized intrinsic delay of an arbitrary static complex CMOS gate (SCCG) based on topology and technology fitting parameters. Our approach is to convert the series-parallel connected MOS transistors into an equivalent RC circuit and calculates the normalized output intrinsic delay by an analytically derived formula. The accuracy of the model is evaluated for several complex gates in various deep submicron (DSM) technologies. The model showed a relatively good accuracy when compared with BSIM3V3 based Spectre simulation. The average error is around ±10% and the maximum error is close to ±13%. Our model contributes to library-free technology mapping.

Keywords

CMOS logic circuits; MOSFET; RC circuits; delay estimation; equivalent circuits; logic gates; DSM technology; deep submicron technology; delay estimation; equivalent RC circuits; library free technology mapping; normalized intrinsic delay model; series-parallel connected MOS transistors; static CMOS complex gates; CMOS technology; Circuit simulation; DH-HEMTs; Delay effects; Delay estimation; Educational institutions; Libraries; MOSFETs; Parasitic capacitance; Semiconductor device modeling;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 2004. NEWCAS 2004. The 2nd Annual IEEE Northeast Workshop on

Print_ISBN

0-7803-8322-2

Type

conf

DOI

10.1109/NEWCAS.2004.1359003

Filename

1359003