AIREN: A Novel Integration of On-Chip and Off-Chip FPGA Networks

The Reconfigurable Computing Cluster Project at the University of North Carolina at Charlotte is investigating the feasibility of using FPGAs as compute nodes to scale to PetaFLOP computing. To date the Spirit cluster, consisting of 64 FPGAs, has been assembled for the initial analysis. One important question is how to efficiently communicate among compute cores on-chip as well as between nodes. Tight integration between both the on-chip and off-chip networks is crucial in obtaining high performance and parallelism while minimizing communication overhead. This paper introduces AIREN - Architecture Independent REconfigurable Network - the integration of an on-chip crossbar switched network with an off-chip k-ary d-cube network and presents the results of integrating AIREN with the Spirit cluster.