Title :
High-speed Viterbi decoder for W-LAN and broadband applications
Author :
Abdul Shakoor, A.R. ; Szwarc, V. ; Kwasniewski, T.A.
Author_Institution :
Commun. Res. Centre, Ottawa, Ont., Canada
Abstract :
This paper presents a configurable Viterbi decoder implementation that meets the requirements of the IEEE 802.11b and 802.16a standards. The programmable very high-speed integrated circuit hardware description language (VHDL) design supports a constraint length (K) 7 Viterbi decoder realization with code rates (R) of 1/2 and 1/3, and trace-back lengths (TBL) of 35 and 50 symbols. To assure high throughput, an architecture incorporating 32 add compare select (ACS) units operating in parallel has been selected. Circuit simulation results, based on an Altera FPGA, are presented and confirm a throughput of 160 Mbps.
Keywords :
Viterbi decoding; broadband networks; circuit simulation; field programmable gate arrays; hardware description languages; integrated circuit design; parallel architectures; very high speed integrated circuits; wireless LAN; Altera FPGA; IEEE 802.11b standards; IEEE 802.16a standards; VHDL; Viterbi decoder; add compare select units; broadband applications; circuit simulation; hardware description language; parallel architectures; trace back length; very high speed integrated circuits; wireless LAN; Circuit simulation; Communication standards; Convolutional codes; Field programmable gate arrays; Hardware design languages; Maximum likelihood decoding; Throughput; Very high speed integrated circuits; Viterbi algorithm; Wireless LAN;
Conference_Titel :
Circuits and Systems, 2004. NEWCAS 2004. The 2nd Annual IEEE Northeast Workshop on
Print_ISBN :
0-7803-8322-2
DOI :
10.1109/NEWCAS.2004.1359005
