A time-domain current model for fully CMOS logic gates

This paper presents two complementary approaches for simulation of mixed-signal CMOS integrated circuits, aiming at estimating crosstalk effects by identifying possible sources of disturbances in analog-digital integrated systems, such as current pulses drawn from voltage supplies. The two simulation algorithms have different levels of detail, so that their computational speed and level of accuracy are different. A simple expression of voltage and current in the pull-up and the pull-down branches of a CMOS logic gate can be derived. Computer simulations demonstrate the feasibility of the proposed approaches.