UVM-based verification of smart-sensor systems

In this contribution, we present a UVM-based methodology for mixed-signal smart-sensor systems. Our approach permits the validation of system functionality before implementation and to verify implementations on various levels of abstraction. The model-based verification approach also helps to build a scalable and re-usable framework, in which assertions and constrained random-stimuli are used to monitor and verify mixed-signal system behavior automatically. Along with the designed UVM -testbench architecture, we describe a novel solution for estimating the power consumption of digital block using application-specific random activity patterns generated during testbench runs.