Title :
Optimizing architecture activity and logic depth for static and dynamic power reduction
Author :
Piguet, Christian ; Schuster, Christian ; Nagel, Jean-Luc
Author_Institution :
CSEM, Neuchatel, Switzerland
Abstract :
As leakage power and total power is a more and more dramatic issue is very deep submicron technologies, this paper explores new design methodologies for designing leakage tolerant digital architectures, based on architectural parameters like activity, logical depth, number of transitions for achieving a given task and total number of gates. Various architectures for a same logic function are compared at very low Vdd and VT that define the optimal total power consumption of each architecture.
Keywords :
logic gates; parallel architectures; power consumption; deep submicron technology; dynamic power reduction; leakage tolerant digital architectures; logic depth; logic function; logic gates; multiplier architecture; power consumption; static power reduction; threshold voltage; Design methodology; Design optimization; Energy consumption; Logic design; Logic functions; Low voltage; MOSFET circuits; Power MOSFET; Threshold voltage; Transistors;
Conference_Titel :
Circuits and Systems, 2004. NEWCAS 2004. The 2nd Annual IEEE Northeast Workshop on
Print_ISBN :
0-7803-8322-2
DOI :
10.1109/NEWCAS.2004.1359011
