Title :
A low on-resistance SOI LDMOS using a recessed source and a trench drain
Author :
Kim, Sung-Lyong ; Yang, Hoie-Yoon ; Choi, Yearn-Ik
Author_Institution :
Sch. of Electron. Eng., Ajou Univ., Suwon, South Korea
Abstract :
An SOI (Silicon-On-Insulator) LD (Lateral Double-diffused) MOS using a recessed source and a trench drain is proposed to reduce the on-resistance and increase the breakdown voltage. The recessed source structure is formed by v-groove etching and the trench drain structure is formed by RIE (Reactive Ion Etching). The characteristics of the proposed LDMOS are numerically calculated by the two-dimensional process simulator, TSUPREM4 and the device simulator, MEDICI. In case of 36.5 V VLDMOS, the on-resistance of the proposed device is decreased by 41% compared with that of the conventional device
Keywords :
power MOSFET; silicon-on-insulator; 36.5 V; MEDICI; SOI LDMOSFET; TSUPREM4; V-groove etching; breakdown voltage; device simulator; numerical simulation; on-resistance; reactive ion etching; recessed source; trench drain; two-dimensional process simulator; Cities and towns; Costs; Doping; Electric breakdown; Etching; Kilns; Medical simulation; Power integrated circuits; Smoothing methods; Voltage;
Conference_Titel :
Microelectronics, 2000. Proceedings. 2000 22nd International Conference on
Conference_Location :
Nis
Print_ISBN :
0-7803-5235-1
DOI :
10.1109/ICMEL.2000.838772
