DocumentCode :
1951645
Title :
AIDA: Automated analog IC design flow from circuit level to layout
Author :
Martins, R. ; Lourenço, N. ; Rodrigues, S. ; Guilherme, J. ; Horta, N.
Author_Institution :
Inst. de Telecomun., Lisbon, Portugal
fYear :
2012
fDate :
19-21 Sept. 2012
Firstpage :
29
Lastpage :
32
Abstract :
This paper presents AIDA, an analog integrated circuit design automation environment, which implements a design flow from a circuit-level specification to a physical layout description. AIDA results from the integration of two in-house tools, namely, GENOM-POF and LAYGEN II. GENOM-POF performs fully automated circuit-level synthesis implemented with a multi-objective multi-constraint optimization approach, which addresses robust design requirements by considering Corners analysis together with an electrical simulator as the evaluation engine. LAYGEN II implements a DRC proved fully automated layout generation based on a sized circuit-level description and high level layout guidelines, described in a technology independent abstract layout template. The expert knowledge is used by LAYGEN II to guide the evolutionary optimization kernels during the automatic layout generation. Moreover, evolutionary computation techniques are extensively used, at both circuit-level and physical-level, as tool to solve design optimization problems. Finally, AIDA environment is demonstrated for the IC design of a classical circuit-level topology and state-of-the-art technology, and validated by industrial simulators and analysis tools, such as, HSPICE® and CALIBRE®.
Keywords :
analogue integrated circuits; evolutionary computation; integrated circuit layout; AIDA environment; CALIBRE; Corners analysis; DRC; GENOM-POF; HSPICE; LAYGEN II; analysis tools; automated analog IC design flow; automated circuit-level synthesis; automatic layout generation; circuit-level specification; circuit-level topology; electrical simulator; evolutionary optimization kernels; expert knowledge; high level layout guidelines; in-house tools; industrial simulators; multiobjective multiconstraint optimization approach; physical layout description; sized circuit-level description; technology independent abstract layout template; Bioinformatics; Design automation; Genomics; Integrated circuits; Layout; Optimization; Robustness; Analog Integrated Circuits; Circuit Level; Design Autonation; Physical Level; Robust Design;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD), 2012 International Conference on
Conference_Location :
Seville
Print_ISBN :
978-1-4673-0685-0
Type :
conf
DOI :
10.1109/SMACD.2012.6339409
Filename :
6339409
Link To Document :
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