DocumentCode :
1951656
Title :
55nm gate CMOS technology using sub-keV ion implantation without through surface oxide
Author :
Sayama, H. ; Miyoshi, H. ; Kawasaki, Y. ; Ota, K. ; Oda, H. ; Kuroi, T. ; Eimori, T. ; Morimmo, H. ; Nakauka, H. ; Fuse, G. ; Nakanishi, K. ; Sebe, A. ; Kishimoto, T. ; Yamada, T. ; Kajiya, A. ; Mayumi, S.
Author_Institution :
Mitsubishi Electric Corporation
fYear :
2002
fDate :
2-3 Dec. 2002
Firstpage :
105
Lastpage :
106
Abstract :
Sub-keV ion implantation without through surface oxide on SDE (source drain extension) rcgion has been dcmonstrated. It is found that sub-keV ion implantation is a uscful technique for fabrication of high performance transistors by rcmoval of surface oxide.
Keywords :
Abstracts; Boron; CMOS process; CMOS technology; Fabrication; Fuses; Ion implantation; Rapid thermal processing; Silicon; Surface resistance;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Junction Technology, 2002. IWJT. Extended Abstracts of the Third International Workshop on
Conference_Location :
Tokyo, Japan
Print_ISBN :
4-89114-028-3
Type :
conf
DOI :
10.1109/IWJT.2002.1225216
Filename :
1225216
Link To Document :
بازگشت