55nm gate CMOS technology using sub-keV ion implantation without through surface oxide
Author :
Sayama, H. ; Miyoshi, H. ; Kawasaki, Y. ; Ota, K. ; Oda, H. ; Kuroi, T. ; Eimori, T. ; Morimmo, H. ; Nakauka, H. ; Fuse, G. ; Nakanishi, K. ; Sebe, A. ; Kishimoto, T. ; Yamada, T. ; Kajiya, A. ; Mayumi, S.
Author_Institution :
Mitsubishi Electric Corporation
fYear :
2002
fDate :
2-3 Dec. 2002
Firstpage :
105
Lastpage :
106
Abstract :
Sub-keV ion implantation without through surface oxide on SDE (source drain extension) rcgion has been dcmonstrated. It is found that sub-keV ion implantation is a uscful technique for fabrication of high performance transistors by rcmoval of surface oxide.
