SOI technology for future SoC

SOI CMOS devices have been investigated for a long time and as the quality of SOI wafers has been improved as the same level of bulk-Si wafers and improvement of the speed performance of CMOS devices is becoming difficult, they have entered the phase of practical use. There are two approaches for the usage of SOI CMOS. One approach is the SOI CMOS in floating-body structure and the other is the one in body-tied structure. In the case of body-tied structure it is possible to realize the layout with the bulk-Si compatibility and to suppress the history effect due to the floating body structure. To keep the compatibility of bulk-Si CMOS technology, we developed the hybrid trench technology, which realizes the body-tied structure for each transistor and full isolation between NMOS and PMOS transistors.