Formal verification of a bus structure modeled in SystemC

In this paper, we present the formal verification of a bus structure modeled in SystemC. SystemC is an emerging system level design and verification language based on C++ object oriented paradigms. The verification approach is based on both abstract interpretation (for model reduction) followed by model checking of some of the bus properties. In the abstraction phase, we statically analyze the SystemC model considered as C++ code augmented by library constructors, components and entities. We also provide a graphical representation of the reduced model, suitable for debugging and verification purposes. We use the Cadence FormalCheck tool to verify designs properties on the abstracted (reduced) bus model translated into Verilog code. While the verification of the original model was not possible to perform, we succeeded in checking all properties on the reduced model.