An efficient methodology for design and verification of an equalizer for a software defined radio

Design and verification of integrated systems involve a variety of CAD tools, which increase design heterogeneity. This paper presents an efficient methodology based on tool integration that regulates the design and verification flow. The methodology aims at solving key issues in building and verifying a functional prototype of a system and in improving design continuity. Using UML, SystemC and Matlab/Simulink, we were able to create a unified design and verification framework. A digital equalizer is used as an example to validate the methodology.