A practical SOC simulation verification solution: robust design and automatic modeling

The complexity of IC system designs and its stringent requirements from market is been making IC design simulation verification being a big challenge for SOC designers. To produce a high quality system in a short design cycle time, system simulation verification must be done in an affordable time. In this paper, the authors introduce a practical IC design simulation verification flow. In the flow, automatic modeling technique is used to create standardized sub-circuit behavioral models for system simulation verification. At the same time, circuit statistically robust design in the flow ensures that the auto-created models well describe the circuit performance and make the verification valid.