An optimized gate oxide breakdown test by activating oxide traps at low fields

Author

Wang, H. ; Michael, C. ; Geha, S. ; Guo, R.S. ; Messick, C. ; Lahri, R.

Author_Institution

Nat. Semicond. Corp., Santa Clara, CA, USA

fYear

1992

fDate

13-16 Dec. 1992

Firstpage

143

Lastpage

146

Abstract

In this paper, an optimized current ramp charge to breakdown test is evaluated. This methodology is more sensitive to oxide defects than the JEDEC recommended Jramp and the constant current Qbd tests due to its relatively slow current ramp at low fields (10MV/cm-13MV/cm). The time required for this test is consistently less than the constant current Jramp Qbd test. This method has been successfully utilized to identify the best Si surface preclean process in our experiment. The results were confirmed by surface roughness and metal impurity content analysis.<>

Keywords

dielectric thin films; electric breakdown of solids; electron traps; hole traps; reliability; semiconductor device testing; semiconductor-insulator boundaries; Si surface preclean process; SiO/sub 2/-Si; current ramp charge to breakdown test; gate oxide breakdown test; low fields; metal impurity content analysis; optimized test; oxide defects; oxide traps activation; surface roughness analysis; Charge carrier lifetime; Dielectric films; Electric breakdown; Reliability; Semiconductor device testing; Semiconductor-insulator interfaces;

fLanguage

English

Publisher

ieee

Conference_Titel

Electron Devices Meeting, 1992. IEDM '92. Technical Digest., International

Conference_Location

San Francisco, CA, USA

ISSN

0163-1918

Print_ISBN

0-7803-0817-4

Type

conf

DOI

10.1109/IEDM.1992.307328

Filename

307328