Record-low 4 mΩ·mm2 specific on-resistance for 20V trench MOSFETs

A process is shown by which both the specific on-resistance R_ds,on and the gate-drain charge density Q_gd can be reduced. Reduction of the R_ds,on is achieved by optimizing the channel profile (p-body) towards a more box-shaped profile. The Q_gd is reduced by going to smaller trench dimensions below the I-line lithography limits, without using deep-UV lithography. For polygonal cell structures, it is shown that narrowing the trenches also gives further R_ds,on reduction. Record values for R_ds,on of 4 mΩ·mm² (at V_gs=10V) have been obtained for a 20V Trench MOSFET with a 2 μm cell pitch. Furthermore, for a conventional 30V Trench MOSFET, we obtained an R_ds,on of 7 mΩ·mm² (at V_gs=10V) by a more box-shaped p-body profile.