A new 600V lateral PMOS device with a buried conduction layer

Author

Disney, D.R.

Author_Institution

Power Integrations, San Jose, CA, USA

fYear

2003

fDate

14-17 April 2003

Firstpage

41

Lastpage

44

Abstract

This paper reports a new 600V lateral PMOSFET with the lowest specific on-resistance ever reported. The novel device is fabricated in bulk silicon using high-energy implantation to form a buried P-type conduction layer within an Nwell. Experimental devices exhibit breakdown voltage of 660V and specific on-resistance of 60 ohm-mm², which is about 50% lower than the state-of-art based on T. Letavic et al. (2002). The device structure, simulations, fabrication process, and experimental results are presented.

Keywords

MOSFET; buried layers; elemental semiconductors; ion implantation; semiconductor device manufacture; semiconductor device models; 600 V; BCPMOS; RESURF; breakdown voltage; bulk silicon; buried P-type conduction layer; buried conduction layer PMOS device; device structure; fabrication process; high-energy implantation; lateral PMOS device; lateral PMOSFET; metal oxide semiconductor field effect transistor; reduced surface field; specific on-resistance; Commercialization; Doping; Fabrication; MOS devices; MOSFET circuits; Phase shift keying; Power integrated circuits; Silicon; Surface resistance; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Power Semiconductor Devices and ICs, 2003. Proceedings. ISPSD '03. 2003 IEEE 15th International Symposium on

Print_ISBN

0-7803-7876-8

Type

conf

DOI

10.1109/ISPSD.2003.1225226

Filename

1225226