First experimental verification of collection length limited gate induced drain leakage

Author

Mii, T. ; Kleinhenz, R. ; Noble, W. ; Johnson, J. ; Bryant, A. ; Jaffe, M.

Author_Institution

IBM Technol. Products, Essex Junction, VT, USA

fYear

1992

fDate

13-16 Dec. 1992

Firstpage

155

Lastpage

158

Abstract

Gate induced drain leakage (GIDL) is recognized as a constraint on the applicable gate-to-drain field imposed by cell leakage in DRAMs and standby power in logic applications. The transport-limited thermal generation model describes GIDL current behavior at gate-induced fields below 5 MV/cm. One unique feature of this model is the dependence of GIDL current on the gate overlap length. This paper presents experimental data which demonstrates the dependence of measured GIDL current on the gate overlap length.<>

Keywords

CMOS integrated circuits; DRAM chips; MOS integrated circuits; cellular arrays; insulated gate field effect transistors; integrated logic circuits; semiconductor device models; DRAMs; GIDL current behavior; cell leakage; collection length limited; gate induced drain leakage; gate overlap length; gate-to-drain field; logic applications; standby power; transport-limited thermal generation model; CMOS integrated circuits; Cellular logic arrays; DRAM chips; Insulated gate FETs; MOS integrated circuits; Semiconductor device modeling;

fLanguage

English

Publisher

ieee

Conference_Titel

Electron Devices Meeting, 1992. IEDM '92. Technical Digest., International

Conference_Location

San Francisco, CA, USA

ISSN

0163-1918

Print_ISBN

0-7803-0817-4

Type

conf

DOI

10.1109/IEDM.1992.307331

Filename

307331