DocumentCode :
1951965
Title :
Systematic generation of performance models of reconfigurable analog circuits
Author :
Velasco-Jiménez, Manuel ; Castro-López, Rafael ; Roca, Elisenda ; Fernández, Francisco
Author_Institution :
Seville Microelectron. Inst., Univ. of Seville, Seville, Spain
fYear :
2012
fDate :
19-21 Sept. 2012
Firstpage :
77
Lastpage :
80
Abstract :
In this work, a systematic technique to generate performance models of reconfigurable analog circuits is presented. The performance models are obtained in the form of multi-mode Pareto-optimal fronts (mm-PoFs), a new type of Pareto-optimal front (PoF) that characterizes the set of different performances that reconfigurable circuits can attain. The technique is based on the use of an evolutionary algorithm (EA) that acts as an optimizer, and the simulator HSPICE to measure the circuit performances. The use of this technique will be illustrated for a wireless multistandard problem, where a reconfigurable op-amp will be considered.
Keywords :
Pareto optimisation; analogue circuits; evolutionary computation; operational amplifiers; EA; HSPICE simulator; evolutionary algorithm; mm-PoF; multimode Pareto-optimal fronts; performance models; reconfigurable analog circuits; reconfigurable op-amp; systematic generation; wireless multistandard problem; Analog circuits; Design methodology; Evolutionary computation; GSM; Power demand; Solid modeling; Standards; Analog circuits; evolutionary algorithms; pareto-optimal fronts; performance models; reconfigurability;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD), 2012 International Conference on
Conference_Location :
Seville
Print_ISBN :
978-1-4673-0685-0
Type :
conf
DOI :
10.1109/SMACD.2012.6339421
Filename :
6339421
Link To Document :
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