Systematic generation of performance models of reconfigurable analog circuits

In this work, a systematic technique to generate performance models of reconfigurable analog circuits is presented. The performance models are obtained in the form of multi-mode Pareto-optimal fronts (mm-PoFs), a new type of Pareto-optimal front (PoF) that characterizes the set of different performances that reconfigurable circuits can attain. The technique is based on the use of an evolutionary algorithm (EA) that acts as an optimizer, and the simulator HSPICE to measure the circuit performances. The use of this technique will be illustrated for a wireless multistandard problem, where a reconfigurable op-amp will be considered.