A variable period clock synthesis (VPCS) architecture for next-generation power-aware SoC applications

This paper, presents a variable period clock synthesis (VPCS) architecture that has the ability to multiply or divide a reference clock frequency on the fly, depending on the application requirements. The VPCS architecture has the advantage of switching from a current clock frequency to a target one within only one clock cycle, thus improving frequency switching delays compared to previous designs. The VPCS design also has the ability to generate any period with any resolution, an important feature that saves power in devices with multiple frequency requirements. A prototype of the VPCS architecture was developed in VHDL and synthesized in CMOS 0.18 μm technology. The design generated clocks with frequencies up to 333.33 MHz. A design aiming at a maximum frequency of 250 MHz has a low power clock generation of 0.16 mW when running at 16.67 MHz, using 16 phases of a 15.625 MHz reference clock. This design is suitable for high speed, energy-efficient portable applications with variable speed needs.