Title :
Optimization of LDMOS array design for SOA and hot carrier lifetime
Author :
Strachan, Andy ; Brisbin, Doug
Author_Institution :
Adv. Process Technol. Dev., National Semicond., Santa Clara, CA, USA
Abstract :
Optimization of LDMOS devices to meet safe operating area (SOA) and hot carrier lifetime targets is a current challenge for process development. This work focuses on novel results in the use of layout techniques and cell design to improve both SOA and hot carrier reliability of LDMOS arrays. Specific improvements to cell based array layouts that increase SOA and hot carrier lifetime for fixed transistor architecture are reported.
Keywords :
CMOS integrated circuits; carrier lifetime; hot carriers; integrated circuit layout; integrated circuit reliability; power MOSFET; power integrated circuits; semiconductor device reliability; LDMOS array design; SOA; cell based array layout; cell design; hot carrier lifetime; hot carrier reliability; laterally diffused metal oxide semiconductor; safe operating area; transistor architecture; BiCMOS integrated circuits; CMOS process; Degradation; Design optimization; Doping; Hot carriers; Impact ionization; Implants; Semiconductor optical amplifiers; Stress;
Conference_Titel :
Power Semiconductor Devices and ICs, 2003. Proceedings. ISPSD '03. 2003 IEEE 15th International Symposium on
Print_ISBN :
0-7803-7876-8
DOI :
10.1109/ISPSD.2003.1225236
