Title :
On-chip signaling for ultra low-voltage 0.13 μm CMOS SOI technology
Author :
Valentian, Alexandre ; Amara, Amara
Author_Institution :
Inst. Superieur d´´Electron., Paris, France
Abstract :
This paper presents a current-mode signaling technique in an ultra low-voltage environment. At power supply voltage VDD below 500 mV, the CMOS gate delay is dominant with regard to the delay in the interconnect. Thus, buffering techniques using inverter chains are not efficient, especially for high data rates. In this paper, we reevaluate the benefits of current sensing for ULV applications and present a new auto-regulated current sensing scheme (ARCS), which allows power savings of more than 55% on a 2 pF interconnect for high data rate signals at almost no performance penalty, comparing to voltage mode signaling. The ARCS scheme has been implemented in a 130 nm partially depleted SOI technology.
Keywords :
CMOS integrated circuits; current-mode circuits; delay circuits; elemental semiconductors; integrated circuit interconnections; low-power electronics; silicon-on-insulator; system-on-chip; 0.13 micron; 130 nm; 2 pF; CMOS SOI technology; CMOS gate delay; Si; autoregulated current sensing method; circuit interconnections; current mode signaling technique; high data rate signals; partially depleted SOI technology; system-on-chip signaling; ultra low voltage environment; CMOS technology; Delay; Immune system; Impedance; Integrated circuit interconnections; Inverters; Power system interconnection; RLC circuits; Transconductance; Voltage;
Conference_Titel :
Circuits and Systems, 2004. NEWCAS 2004. The 2nd Annual IEEE Northeast Workshop on
Print_ISBN :
0-7803-8322-2
DOI :
10.1109/NEWCAS.2004.1359049
