Title :
A simplified and meaningful crack propagation model in silicon for microelectronic power devices
Author :
Calvez, D. ; Roqueta, F. ; Jacques, S. ; Ducret, S. ; Bechou, L. ; Ousten, Y.
Abstract :
Wafer handling during the manufacturing process introduces micro-cracks and flaws at the wafer edge. The aim of this work was to determine whether an initial crack would be able to propagate through the silicon active region of power devices when it is subjected to high electro-thermal loads during its application or during thermal cycling tests. We have determined the most critical crack propagation cases. These have been simulated using the ANSYS® FEA software and energy release rate G (ERR) has been calculated for different crack lengths, locations, or thermal loads, and then compared to the silicon critical ERR of the silicon. Temperature profiles that reproduce the typical device operation conditions are retrieved with electro-thermal simulation. Failure analysis performed on these power devices has revealed some typical propagation paths.
Keywords :
failure analysis; finite element analysis; microcracks; semiconductor device reliability; semiconductor device testing; semiconductor technology; ANSYS FEA software; crack length; critical crack propagation model; device operation condition; electrothermal loads; electrothermal simulation; energy release rate; failure analysis; initial crack; manufacturing process; microcracks; microelectronic power devices; propagation path; silicon active region; silicon critical ERR; temperature profiles; thermal cycling test; wafer edge; wafer handling; Assembly; Bifurcation; Copper; Metallization; Passivation; Silicon;
Conference_Titel :
Thermal, Mechanical and Multi-Physics Simulation and Experiments in Microelectronics and Microsystems (EuroSimE), 2012 13th International Conference on
Conference_Location :
Cascais
Print_ISBN :
978-1-4673-1512-8
DOI :
10.1109/ESimE.2012.6191721
