Asynchronous ADC/microprocessor interface

Author

Zhu, Tao ; Kong, Xiaohua ; Negulescu, Radu

Author_Institution

Dept. of Electr. & Comput. Eng., McGill Univ., Montreal, Que., Canada

fYear

2004

fDate

20-23 June 2004

Firstpage

193

Lastpage

196

Abstract

System-on-chip technology raises challenges when smooth interfacing between different functional systems is required. This paper presents the design of an asynchronous interface between irregular sampling and asynchronous microprocessor. The target of this design is to interface an asynchronous microprocessor with front-end devices with high-speed and low-power operation modes depending on the sampling rate. We use GasP FIFOs, as well as several custom-designed modules to implement this interface. Simulation results in Hspice for a CMOSP18 technology shows stable operation of up to 3.1 giga data items/sec (GDI/s).

Keywords

CMOS integrated circuits; analogue-digital conversion; asynchronous circuits; circuit simulation; high-speed integrated circuits; integrated circuit design; logic design; low-power electronics; microprocessor chips; system-on-chip; CMOS technology; Hspice simulation; asynchronous ADC-microprocessor interface; front end devices; high speed circuits; irregular sampling; low power electronics; system-on-chip technology; CMOS technology; Circuits; Communication system control; Data communication; Microprocessors; Protocols; Sampling methods; Signal sampling; System-on-a-chip; Wires;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 2004. NEWCAS 2004. The 2nd Annual IEEE Northeast Workshop on

Print_ISBN

0-7803-8322-2

Type

conf

DOI

10.1109/NEWCAS.2004.1359056

Filename

1359056