Current density aware algorithm for net generation in analog high current application

In deep submicron VLSI circuits, excessive current density in interconnects is a major concern for analog high current application. If current over maximum density is not effectively mitigated, this can lead to phenomena like electromigration, voltage drop and electrical overload. It is a hot topic of interest in modern circuits due to the decrease of metal track sizes while high currents are necessary in automotive or mobile applications. In this paper, an algorithm considering current constraints for net generation is presented. It determines all branch currents and proposes a routing for signal nets with current-dependent wire width. First, the phenomena of electromigration and voltage drop are introduced. The current constrained wire planning algorithm is presented and shows results improved on average by about 10% for area and almost 27% for CPU time compared with existing solution.