Title :
Testing oriented analysis of CMOS ICs with opens
Author :
Maly, W. ; Nag, P.K. ; Nigh, P.
Author_Institution :
Dept. of Electr. & Comput. Eng., Carnegie-Mellon Univ., Pittsburgh, PA, USA
Abstract :
In a typical approach to VLSI testing, open faults are modeled by the transistor-stuck-open fault model or are not explicitly covered at all. It is shown that functional faults caused by opens, i.e. by regions with missing material, cannot be modeled well by a transistor stuck-open. It is also shown that the majority of opens which occur in CMOS static circuits manifest themselves as timing faults. The analysis of the behavior of a CMOS transistor with a floating gate indicates it acts as a weakly ´on´ active load, and therefore an open gate cannot be detected by stuck-fault testing but could be detected by monitoring the static current through the power buses.<>
Keywords :
CMOS integrated circuits; VLSI; circuit analysis computing; fault location; integrated circuit testing; CMOS ICs; VLSI testing; active load; floating gate; functional faults; missing material; open gate; power bus static current monitoring; static circuits; testing oriented analysis; timing faults; transistor-stuck-open fault model; CMOS technology; Circuit analysis; Circuit faults; Circuit testing; Fault detection; MOSFETs; Monitoring; Semiconductor device modeling; Timing; Very large scale integration;
Conference_Titel :
Computer-Aided Design, 1988. ICCAD-88. Digest of Technical Papers., IEEE International Conference on
Conference_Location :
Santa Clara, CA, USA
Print_ISBN :
0-8186-0869-2
DOI :
10.1109/ICCAD.1988.122525
