A poly-buffer recessed LOCOS process for 256 Mbit DRAM cells

Author

Shimizu, N. ; Naito, Y. ; Itoh, Y. ; Shibata, Y. ; Hashimoto, K. ; Nishio, M. ; Asai, A. ; Ohe, K. ; Umimoto, H. ; Hirofuji, Y.

Author_Institution

Semicond. Res. Center, Matsushita Electr. Ind. Co. Ltd., Osaka, Japan

fYear

1992

fDate

13-16 Dec. 1992

Firstpage

279

Lastpage

282

Abstract

A new isolation technology, called PBR LOCOS (Poly Buffer Recessed LOCOS) process, has been developed for a 256Mbit DRAM with 0.72 mu m/sup 2/ cell. The features of the PBR LOCOS process are low bird´s beak encroachment and defects free isolation, which are achieved by using shallow recess etching, buffer polysilicon, and silicon nitride sidewall. It is formed that the shallow recess etching provides high punch-through voltage of parasitic field transistors. The PBR LOCOS process allows the fabrication of 256Mbit DRAM cells.<>

Keywords

DRAM chips; MOS integrated circuits; elemental semiconductors; etching; integrated circuit technology; semiconductor technology; silicon; silicon compounds; substrates; 256 Mbit; DRAM cells; IC technology; LPCVD; Si; Si-Si/sub 3/N/sub 4/; Si/sub 3/N/sub 4/ film; buffer polysilicon; high punch-through voltage; isolation technology; parasitic field transistors; poly-buffer recessed LOCOS; shallow recess etching; silicon nitride sidewall; DRAM chips; Etching; Integrated circuit fabrication; MOS integrated circuits; Semiconductor device fabrication; Silicon; Silicon compounds;

fLanguage

English

Publisher

ieee

Conference_Titel

Electron Devices Meeting, 1992. IEDM '92. Technical Digest., International

Conference_Location

San Francisco, CA, USA

ISSN

0163-1918

Print_ISBN

0-7803-0817-4

Type

conf

DOI

10.1109/IEDM.1992.307360

Filename

307360