DocumentCode
1952498
Title
A high speed 512-bit modular multiplier for a RSA chip
Author
Shao, Jiang ; Kort, Skander
Author_Institution
Dept. of Electr. & Comput. Eng., Concordia Univ., Montreal, Que., Canada
fYear
2004
fDate
20-23 June 2004
Firstpage
237
Lastpage
240
Abstract
This paper describes a modular multiplication circuit. The circuit is used in a RSA encryption/decryption chip. The proposed multiplier implements an iterative-addition algorithm using a CSA structure. Radix-4 Booth encoding was adopted in order to reduce the number of algorithm iterations by half. The design applies the R-L binary modular exponentiation method to achieve higher performance.
Keywords
carry logic; encoding; field programmable gate arrays; iterative methods; multiplying circuits; public key cryptography; R-L binary modular exponentiation method; RSA encryption-decryption chip; carry save adder structure; field programmable gate arrays; high speed modular multiplier; iterative addition algorithm; modular multiplication circuit; radix-4 booth encoding; Adders; Algorithm design and analysis; Circuits; Clocks; Encoding; Field programmable gate arrays; Hardware; Public key; Public key cryptography; Security;
fLanguage
English
Publisher
ieee
Conference_Titel
Circuits and Systems, 2004. NEWCAS 2004. The 2nd Annual IEEE Northeast Workshop on
Print_ISBN
0-7803-8322-2
Type
conf
DOI
10.1109/NEWCAS.2004.1359074
Filename
1359074
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