CVD Cu interconnections for ULSI

Author

Cho, J.S.H. ; Ho-Kyu Kang ; Asano, I. ; Wong, S.S.

Author_Institution

Center for Integrated Syst., Stanford Univ., CA, USA

fYear

1992

fDate

13-16 Dec. 1992

Firstpage

297

Lastpage

300

Abstract

CVD Cu has been investigated as an interconnection material. The Cu films have excellent step coverage due to the very low sticking coefficient of 0.015 of the precursor, Cu/sup 1+/(tmvs) (hfac). High aspect ratio trenches and vias can be conformally filled without formation of keyholes. Using etchback processes, lines and plugs can be formed. At temperatures typically encountered in back-end processing, no significant diffusion of Cu through several commonly used inter-metal dielectrics and TiW is observed. CVD Cu interconnections have been incorporated into a CMOS process. No degradation in device characteristics due to Cu is detected.<>

Keywords

CMOS integrated circuits; VLSI; chemical vapour deposition; copper; integrated circuit technology; metallisation; CMOS process; CVD; Cu; ULSI; aspect ratio; back-end processing; device characteristics; etchback processes; inter-metal dielectrics; interconnection material; step coverage; sticking coefficient; trenches; vias; CMOS integrated circuits; CVD; Copper; Integrated circuit fabrication; Metallization; Very-large-scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

Electron Devices Meeting, 1992. IEDM '92. Technical Digest., International

Conference_Location

San Francisco, CA, USA

ISSN

0163-1918

Print_ISBN

0-7803-0817-4

Type

conf

DOI

10.1109/IEDM.1992.307364

Filename

307364