A new architecture for area and power efficient, high conversion rate successive approximation ADCs

A new high-speed successive approximation analog-to-digital converter architecture is presented. Two bits extraction in each clock cycle is the key idea to double the conversion speed. Generating reference levels for three comparators with only two DACs, is another novelty of the new architecture. The simulation results for the designed 10-bit ADC show that in same conversion rate, better figure of merit value, 40% and 7% reduction in chip size and power consumption is achievable over the conventional SA-ADC architecture.