Title :
Performance estimation framework for FPGA-based processors
Author :
Aung, Yan Lin ; Lam, Siew Kei ; Srikanthan, Thambipillai
Author_Institution :
Sch. of Comput. Eng., NTU, Singapore, Singapore
Abstract :
Modern FPGA devices can implement a variety of processors with numerous configurable options. Rapid performance estimation of FPGA processors plays a vital role in embedded systems design to select a processor that best fits the application requirements. Traditional performance evaluation techniques such as running the software application on the target processor or using cycle accurate instruction set simulator are time-consuming and poses a threat in meeting the stringent time-to-market pressure. In this paper, we propose a framework to rapidly estimate the performance of a wide range of FPGA processors. The proposed method relies on the LLVM compiler infrastructure and its backend code generator to accurately estimate the software performance within seconds. Experimental results show that the proposed framework can reliably estimate the performance of a widely used FPGA processor with an average accuracy of over 90% for a number of benchmark applications.
Keywords :
field programmable gate arrays; performance evaluation; program compilers; FPGA-based processors; LLVM compiler infrastructure; backend code generator; embedded systems design; performance estimation framework; Assembly; Clocks; Estimation; Field programmable gate arrays; Hardware; Program processors;
Conference_Titel :
Field-Programmable Technology (FPT), 2010 International Conference on
Conference_Location :
Beijing
Print_ISBN :
978-1-4244-8980-0
DOI :
10.1109/FPT.2010.5681448