DocumentCode
1952582
Title
A 0.25-micron Smart Power Technology optimized for wireless and consumer applications
Author
Zhu, R. ; Parthasarathy, V. ; Khemka, V. ; Bose, A. ; Roggenbauer, T. ; Lee, G. ; Baumert, B. ; Hui, P. ; Rodriguez, Paul ; Collins, D.
Author_Institution
SPS, Motorola Inc., Tempe, AZ, USA
fYear
2003
fDate
14-17 April 2003
Firstpage
178
Lastpage
181
Abstract
In this paper simultaneous optimization of 4.5-5.5V N and PMOS devices, 20-30V NLDMOS and NPN and PNP bipolar devices in a 0.25 μm Smart Power Technology for portable wireless and consumer applications is discussed. With the addition of two designated wells, ultra-low resistance N and PMOS devices with good analog characteristics, best in class 30V NLDMOS as well as integrated high performance NPN and PNP bipolar devices is demonstrated.
Keywords
circuit optimisation; consumer electronics; portable instruments; power integrated circuits; 0.25 micron; 20 to 30 V; 4.5 to 5.5 V; PMOS device; analog characteristic; bipolar device; consumer application; designated well; portable wireless; simultaneous optimization; smart power technology; Batteries; CMOS technology; Circuits; Energy management; Leakage current; Logic devices; Low voltage; MOS devices; Medium voltage; Regulators;
fLanguage
English
Publisher
ieee
Conference_Titel
Power Semiconductor Devices and ICs, 2003. Proceedings. ISPSD '03. 2003 IEEE 15th International Symposium on
Print_ISBN
0-7803-7876-8
Type
conf
DOI
10.1109/ISPSD.2003.1225258
Filename
1225258
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