Title :
Automatic modeling of switch-level networks using partial orders
Author :
Agrawal, P. ; Robinson, S.H. ; Szymanski, T.G.
Author_Institution :
AT&T Bell Lab., Murray Hill, NJ, USA
Abstract :
A key idea in switch-level simulation is the use of a total ordering of signal strengths to resolve conflicts between opposing signals. For many circuits, however, it is not possible to assign such strengths to circuit elements in a logically consistent fashion without user intervention. It is shown that the use of a partial ordering of strengths avoids these difficulties and allows modeling to be done automatically. The authors also discuss the need to minimize the number of distinct strengths needed to model a circuit, because simulation times are affected by the number of strengths being used. This is especially important for compiled switch-level simulators that generate representations whose size is proportional to the number of strengths. Statistics on the application of these ideas to industrial chips are presented.<>
Keywords :
circuit analysis computing; digital simulation; integrated logic circuits; logic CAD; automatic modelling; circuit elements; compiled simulators; conflict resolution; industrial chips; opposing signals; partial orders; signal strengths; simulation times; switch-level networks; switch-level simulation; user intervention; Capacitance; Circuit optimization; Circuit simulation; Logic circuits; Mathematical model; Pathology; Production; Signal resolution; Statistics; Switching circuits;
Conference_Titel :
Computer-Aided Design, 1988. ICCAD-88. Digest of Technical Papers., IEEE International Conference on
Conference_Location :
Santa Clara, CA, USA
Print_ISBN :
0-8186-0869-2
DOI :
10.1109/ICCAD.1988.122526