Multiclass large scale ATM switch with QoS guarantee

This paper proposes a growable switch architecture with multiple modules comprising a CORE module to support highspeed switching and EDGE modules with large buffers, providing a large number of traffic classes. For open-loop traffic such as CBR and VBR, the proposed switch uses a weighted fair queueing scheduler at each EDGE buffer module based on the equivalent bandwidth allocated by the call admission control (CAC). On the other hand, for best effort class services (e.g., ABR and UBR), closed-loop control using adaptive rate control at the actual source and at the virtual source queue of the input EDGE module is proposed to avoid internal congestion and to achieve fair throughput performance among the flows competing on the same link. Simulation results show that the proposed architecture achieves ATM switches having hundreds of Gbps capacity, while providing a large number of QoS classes with high throughput and fair sharing of bandwidth by all flows