• DocumentCode
    1952618
  • Title

    GLACIER: a hot carrier gate level circuit characterization and simulation system for VLSI design

  • Author

    Wu, Lifeng ; Fang, Jingkun ; Yonezawa, Hirokazu ; Kawakami, Yoshiyuki ; Iwanishi, Nobufusa ; Yan, Heting ; Chen, Ping ; Chen, Alvin I-Hsien ; Koike, Norio ; Okamoto, Yoshifumi ; Yeh, Chune-Sin ; Liu, Zhihong

  • Author_Institution
    BTA Technol. Inc., San Jose, CA, USA
  • fYear
    2000
  • fDate
    2000
  • Firstpage
    73
  • Lastpage
    79
  • Abstract
    Gate level circuit simulation on hot carrier degradation is introduced for the first time by the GLACIER system presented in this paper. The inherent advantages such as high speed and high capacity of the gate level simulation as compared to the traditional transistor level hot carrier simulation makes the design-in reliability simulation possible and practical for the deep submicron VLSI circuit designs with millions of transistors. By virtue of a unique ratio based modeling technique, GLACIER system provides a very high accuracy which is mostly within 1% difference of transistor level hot carrier simulation
  • Keywords
    circuit simulation; hot carriers; integrated circuit design; integrated circuit modelling; integrated circuit reliability; GLACIER; VLSI design; deep submicron VLSI circuit; design-in reliability simulation; hot carrier gate level circuit characterization; ratio based modeling technique; Circuit simulation; Circuit synthesis; Degradation; Electron traps; Hot carriers; Large scale integration; Libraries; MOSFET circuits; Timing; Very large scale integration;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Quality Electronic Design, 2000. ISQED 2000. Proceedings. IEEE 2000 First International Symposium on
  • Conference_Location
    San Jose, CA
  • Print_ISBN
    0-7695-0525-2
  • Type

    conf

  • DOI
    10.1109/ISQED.2000.838857
  • Filename
    838857