Cache coherence support in a split-transaction bus for prototyping of system-on-chip multiprocessors

This paper describes the implementation of a split-transaction bus with cache coherence support for use in prototyping of system-on-chip multiprocessors. The bus provides fair arbitration for separate address and data lines. The bus interface for each device on the bus includes a table for tracking all outstanding requests in order to match responses to requests and also to prevent coherence conflicts between requests from different sources. Coherence is also maintained for writeback buffers associated with each processor. A memory inhibit signal is used to enforce coherence when a request matches a modified cache block in a processor cache or writeback buffer. A VHDL implementation for logic simulation is used to verify the functionality of the bus with multiple processors and memory units, leading to synthesis for rapid prototyping in programmable logic.