Title :
Realization of vertical P+ walls through-wafer for bi-directional current and voltage power integrated devices
Author :
Sanchez, J.-L. ; Scheid, E. ; Austin, P. ; Breil, M. ; Carriere, H. ; Dubreuil, P. ; Imbernon, E. ; Rossel, F. ; Rousset, B.
Author_Institution :
LAAS, CNRS, Toulouse, France
Abstract :
P+ walls through wafer can be considered as a region key in the 3D architecture of new bi-directional current and voltage power integrated devices. In this paper, we demonstrate the possibility of fabricating these P+ walls combining the deep RIE of silicon and deposit of boron doped polysilicon.
Keywords :
boron; elemental semiconductors; power integrated circuits; power semiconductor devices; silicon; sputter etching; Si:B; bi-directional current; boron doped polysilicon; deep RIE; vertical P+ walls through-wafer; voltage power integrated device; Anodes; Bidirectional control; Boron; Cathodes; Energy conversion; Etching; Power semiconductor devices; Silicon; Thyristors; Voltage;
Conference_Titel :
Power Semiconductor Devices and ICs, 2003. Proceedings. ISPSD '03. 2003 IEEE 15th International Symposium on
Print_ISBN :
0-7803-7876-8
DOI :
10.1109/ISPSD.2003.1225262
