Title :
Novel polysilicon/TiN stacked-gate structure for fully-depleted SOI/CMOS
Author :
Jeong-Mo Hwang ; Pollack, G.
Author_Institution :
Semicond. Process & Design Center, Texas Instrum. Inc., Dallas, TX, USA
Abstract :
Fully-depleted SOI/CMOS transistors were fabricated using titanium-nitride (TiN) gates with near midgap work-function in order to optimize the p- and n-channel threshold voltages for operation at low supply voltage. To simplify the process as well as to minimize the strain, a novel gate structure was used in which a thick polysilicon (300 nm) was stacked on a thin TiN layer (<50 nm). Excellent symmetrical subthreshold characteristics were obtained with relatively low values of threshold voltage and low off-state leakages. The subthreshold swing, transconductance, and saturation drain current were comparable with those for conventional n/sup +//p/sup +/ polysilicon gates. In addition, hot-carrier stress results indicate no significant differences from the poly-gate cases.<>
Keywords :
CMOS integrated circuits; elemental semiconductors; integrated circuit technology; semiconductor technology; semiconductor-insulator boundaries; silicon; titanium compounds; 300 nm; 50 nm; Si; TiN; TiN gates; fully-depleted SOI/CMOS; hot-carrier stress; n-channel threshold voltages; near midgap work-function; off-state leakages; p-channel threshold voltages; polysilicon/TiN stacked-gate structure; saturation drain current; strain; subthreshold swing; symmetrical subthreshold characteristics; thick polysilicon; thin TiN layer; transconductance; CMOS integrated circuits; Integrated circuit fabrication; Semiconductor device fabrication; Semiconductor-insulator interfaces; Silicon; Titanium compounds;
Conference_Titel :
Electron Devices Meeting, 1992. IEDM '92. Technical Digest., International
Conference_Location :
San Francisco, CA, USA
Print_ISBN :
0-7803-0817-4
DOI :
10.1109/IEDM.1992.307375
