DocumentCode :
1952842
Title :
Enabling DIR (Designing-In-Reliability) through CAD capabilities
Author :
Kang, Wei ; Riley, Jeff ; Doman, D. ; Cano, Frank
fYear :
2000
fDate :
2000
Firstpage :
151
Lastpage :
156
Abstract :
Chip designs are continuously getting larger and more complex. In response to these trends, design methodologies and tool requirements used in recent high-performance designs have been changing rapidly. A Design-In Reliability (DIR) Team was formed at SEMATECH and is composed of DIR and CAD tool experts from the member companies. The team´s primary goals are to define and develop tool requirement needs of the members and to communicate those needs to the EDA industry, in turn fostering development of new and improved tools. In this paper, the DIR project goals and recommendations are presented along with prioritized tool needs or gaps. The tool gaps are put in two categories: CAD tool/data interface and DIR point solutions. CAD tool/data interface deals with core design tools that enable correct-by-construction such as reliability-constraint place-and-route tools. The DIR point solutions refer to reliability simulation or verification tools. Moreover, the high-level tool requirements on top five prioritized tool requirements are presented. In addition, the maturity matrix of DIR tool capabilities is presented in order to show both current and future DIR tool gaps. Also, a high-level roadmap of the team and future projects is presented
Keywords :
circuit CAD; circuit layout CAD; integrated circuit design; integrated circuit reliability; network routing; CAD capabilities; CAD tool/data interface; EDA industry; IC design; SEMATECH; chip designs; core design tools; design methodology; designing-in-reliability; high-level roadmap; high-level tool requirements; reliability simulation; reliability-constraint place/route tools; tool requirements; verification tools; Chip scale packaging; Costs; Design automation; Design methodology; Electrical capacitance tomography; Electronic design automation and methodology; Instruments; Integrated circuit interconnections; Risk analysis;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Quality Electronic Design, 2000. ISQED 2000. Proceedings. IEEE 2000 First International Symposium on
Conference_Location :
San Jose, CA
Print_ISBN :
0-7695-0525-2
Type :
conf
DOI :
10.1109/ISQED.2000.838868
Filename :
838868
Link To Document :
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