A low on resistance 700V charge balanced LDMOS with intersected WELL structure

A new 700V rate charge balanced LDMOS structure is proposed. The key feature of this structure is the intersected N-Well and P-Well that divides drift region into multi parallel conduction path. Ron,sp can be reduced by considerably high doped N-Well region and surface electric field can be dispersed by each Well junction. Ron,sp of the proposed LDMOS is reduced by 55% compared with conventional LDMOS. This value nearly gets to the limit of LDMOS made by bulk silicon. The surface electric field that can cause fatal failure of LDMOS in reliability characteristics is decreased by 30% compared with conventional LDMOS. The position occurring breakdown was moved from surface to bulk below drain contact in the proposed LDMOS.