A low on resistance 700V charge balanced LDMOS with intersected WELL structure

Author

Kim, M.H. ; Kim, J.J. ; Choi, Y.S. ; Jeon, C.K. ; Kim, S.L. ; Kang, H.S. ; Song, C.S.

Author_Institution

Fairchild Semicond., Kyonggi-Do, South Korea

fYear

2003

fDate

14-17 April 2003

Firstpage

220

Lastpage

223

Abstract

A new 700V rate charge balanced LDMOS structure is proposed. The key feature of this structure is the intersected N-Well and P-Well that divides drift region into multi parallel conduction path. Ron,sp can be reduced by considerably high doped N-Well region and surface electric field can be dispersed by each Well junction. Ron,sp of the proposed LDMOS is reduced by 55% compared with conventional LDMOS. This value nearly gets to the limit of LDMOS made by bulk silicon. The surface electric field that can cause fatal failure of LDMOS in reliability characteristics is decreased by 30% compared with conventional LDMOS. The position occurring breakdown was moved from surface to bulk below drain contact in the proposed LDMOS.

Keywords

electric resistance; heavily doped semiconductors; power MOSFET; power integrated circuits; semiconductor device models; semiconductor device reliability; 700 V; balanced LDMOS; bulk silicon; drain contact; drift region; intersected WELL structure; multi parallel conduction path; reliability characteristic; surface electric field; Breakdown voltage; Contacts; Doping; Electric breakdown; Electric resistance; Electrical resistance measurement; Energy consumption; Power integrated circuits; Silicon; Surface resistance;

fLanguage

English

Publisher

ieee

Conference_Titel

Power Semiconductor Devices and ICs, 2003. Proceedings. ISPSD '03. 2003 IEEE 15th International Symposium on

Print_ISBN

0-7803-7876-8

Type

conf

DOI

10.1109/ISPSD.2003.1225268

Filename

1225268