Robust design of a dynamically controlled low-power level-up shifter operating up to 300 V

Author

Huang, Zhengrong ; Savaria, Yvon ; Sawan, Mahamad

Author_Institution

Groupe de Recherche en Microelectron., Ecole Polytech. de Montreal, Que., Canada

fYear

2004

fDate

20-23 June 2004

Firstpage

321

Lastpage

324

Abstract

A new low-power level-up shifter circuit is presented. This circuit produces a digital output signal in the 0-300 V range from a digital input signal in the 0-5 V range. The proposed circuit reduces power through two key features: dynamic charge control reduces the power dissipated in the level-up stage, and a "break before make" logic reduces the short-circuit power of the output stage. Detailed design methodology and optimized circuits for different voltage ranges are described in this paper. This circuit is designed under DALSA semiconductor\´s 0.8 μm 5 V/HV CMOS/DMOS technology. Simulation results validate its operation and performance.

Keywords

CMOS digital integrated circuits; integrated circuit design; low-power electronics; power integrated circuits; semiconductor technology; voltage multipliers; 0 to 300 V; 0.8 micron; DALSA semiconductor CMOS technology; DALSA semiconductor DMOS technology; break before make logic; digital input signal; digital output signal; dynamic charge control; low power level-up shifter circuits; power dissipation; short circuit power; CMOS process; CMOS technology; Driver circuits; Flat panel displays; Logic circuits; Logic devices; Plasma displays; Power supplies; Robust control; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 2004. NEWCAS 2004. The 2nd Annual IEEE Northeast Workshop on

Print_ISBN

0-7803-8322-2

Type

conf

DOI

10.1109/NEWCAS.2004.1359096

Filename

1359096