A high-performance low-complexity bipolar technology using selective collector compensation

This paper describes a novel bipolar technology which achieves very high ECL performance while maintaining low process complexity, large fabrication tolerances, and full CMOS compatibility. The high NPN BJT performance is achieved by using a p-type collector well rather than a conventional n-well. This allows a large decrease in the junction capacitances of the BJT. Furthermore, the BJT can be merged in the same well as the diffused ECL load resistor, resulting in a substantial area savings and further performance improvement. A minimum power-delay product of 50 fJ for a standard ECL gate is demonstrated for these devices.<>