DocumentCode :
1953029
Title :
A roadmap to low cost bumping for DCA, COF, CSP and BGA [flip chip]
Author :
Zakel, E. ; Teutsch, T.
Author_Institution :
Pac Tech-Packaging Technol. GmbH, Germany
fYear :
1998
fDate :
27-29 Apr 1998
Firstpage :
55
Lastpage :
62
Abstract :
Flip chip (FC) technology is gaining an increased level of importance for a variety of applications based on flip chip on board or flip chip in package. The first driving force for the introduction of this technology was the need to achieve increased speed and performance along with higher I/O count. A breakthrough, however, will be the use of flip chip due to cost reduction. For this aim, it is essential to use low cost bumping techniques in combination with an assembly method compatible with existing SMT processes. The FC techniques presented in this paper are all based on an electroless Ni/Au bumping process which has been developed by TUB/IZM and implemented into production by Pac Tech. This paper shows a roadmap based on electroless nickel/gold bumping for all flip chip interconnection technologies used in industry at present. Additionally, the roadmap to future developments in semiconductor industry based on 300 mm wafers and the use of new pad metallisations such as copper is shown. The compatibility of electroless nickel bumping in particular with these new technologies to be implemented in wafer manufacturing within the next millenium shows that this key technology offers a roadmap to flip chip technology not only for the products and wafer technologies in use at present, but also for next generation wafer technologies
Keywords :
ball grid arrays; chip scale packaging; chip-on-board packaging; electroless deposition; flip-chip devices; gold; integrated circuit interconnections; integrated circuit metallisation; microassembling; nickel; surface mount technology; technological forecasting; 300 mm; BGA; COF; CSP; Cu pad metallisations; DCA; FC techniques; Ni-Au; SMT process compatibility; assembly method; bumping techniques; chip on flex; cost reduction; direct chip attach; electroless Ni/Au bumping process; electroless nickel bumping; electroless nickel/gold bumping; flip chip bumping; flip chip in package; flip chip interconnection; flip chip on board; flip chip technology; package I/O count; semiconductor industry; wafer manufacturing; wafer size; wafer technology; Assembly; Chip scale packaging; Costs; Electronics industry; Flip chip; Gold; Manufacturing industries; Nickel; Production; Surface-mount technology;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Electronics Manufacturing Technology Symposium, 1998. IEMT-Europe 1998. Twenty-Second IEEE/CPMT International
Conference_Location :
Berlin
Print_ISBN :
0-7803-4520-7
Type :
conf
DOI :
10.1109/IEMTE.1998.723060
Filename :
723060
Link To Document :
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