Title :
Synthesizable SystemVerilog Assertions as a Methodology for SoC
Author :
Kastelan, Ivan ; Krajacevic, Zoran
Author_Institution :
Fac. of Tech. Sci., Univ. of Novi Sad, Novi Sad, Serbia
Abstract :
This paper presents one implementation of the Open Control Protocol (OCP) monitoring on the synthesized FPGA design using the implemented library of Synthesizable SystemVerilog Assertions (SSVA). The SSVA library is developed using the layer structure of SystemVerilog assertions. It is used in implementation of the monitors for two profiles of the OCP. SSVA library and OCP monitors are then functionally verified in simulator using the test case of the processor-memory communication. The test case is then synthesized on CHIPit Platinum Edition FPGA. The implemented library and monitors can be used in many commercial and educational projects due to their simplicity and low FPGA area usage.
Keywords :
field programmable gate arrays; hardware-software codesign; logic CAD; software libraries; system-on-chip; CHIPit platinum edition FPGA; FPGA design; SSVA library; SoC verification; commercial projects; educational projects; open control protocol monitoring; processor-memory communication; synthesizable systemverilog assertions; Application specific integrated circuits; Combinational circuits; Computerized monitoring; Control system synthesis; Delay; Design engineering; Field programmable gate arrays; Libraries; Protocols; Testing; Assertion; FPGA; OCP; SystemVerilog;
Conference_Titel :
Engineering of Computer Based Systems, 2009. ECBS-EERC '09. First IEEE Eastern European Conference on the
Conference_Location :
Novi Sad
Print_ISBN :
978-1-4244-4677-3
Electronic_ISBN :
978-0-7695-3759-7
DOI :
10.1109/ECBS-EERC.2009.19
