Title :
High-level substrate current effects in P--epitaxy/P+-substrate Smart Power Technologies
Author :
Laine, J.P. ; Bertolini, L. ; Bafleur, M. ; Lochot, C.
Author_Institution :
LAAS, CNRS, Toulouse, France
Abstract :
Substrate current injection, and in particularly minority carrier injection, is one of the major redesign causes in Smart Power technology. This substrate parasitic current induces unexpected failure system such as latchup in CMOS circuitry. The P+-substrate is proposed to reduce it. This reduction depends on the P--epitaxy thickness over the P+-substrate versus the injection level. An original physical mechanism against this parasitic current is presented in this paper.
Keywords :
CMOS integrated circuits; minority carriers; power integrated circuits; semiconductor epitaxial layers; substrates; CMOS circuitry; failure system; high-level substrate current effect; injection level; minority carrier injection; physical mechanism; smart power technology; substrate current injection; substrate parasitic current; Bipolar transistors; CMOS analog integrated circuits; CMOS process; CMOS technology; Current measurement; Isolation technology; Power measurement; Semiconductor diodes; Signal processing; Substrates;
Conference_Titel :
Power Semiconductor Devices and ICs, 2003. Proceedings. ISPSD '03. 2003 IEEE 15th International Symposium on
Print_ISBN :
0-7803-7876-8
DOI :
10.1109/ISPSD.2003.1225276
