• DocumentCode
    1953184
  • Title

    A versatile, SOI BiCMOS technology with complementary lateral BJT´s

  • Author

    Parke, S. ; Assaderaghi, F. ; Jian Chen ; King, J. ; Chenming Hu ; Ko, P.K.

  • Author_Institution
    Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA
  • fYear
    1992
  • fDate
    13-16 Dec. 1992
  • Firstpage
    453
  • Lastpage
    456
  • Abstract
    A silicon-on-insulator, fully-complementary BiCMOS process has been developed for realizing high-performance circuit operation in the sub-3.3 V power supply regime. Complementary, double-diffused lateral BJTs and fully-overlapped, asymmetrical DDD MOSFETs have been successfully integrated in a 10-mask process by utilizing the process simplifications that are unique to thin-film SOI substrates. The BJTs exhibit the highest lateral current gains reported to date, with h/sub fe/=120 and 225 for the NPN and PNP, respectively. NPN f/sub t/=4.5 GHz was achieved, and f/sub t/>20 GHz is possible with an improved layout. The MOSFETs demonstrate excellent short-channel behavior down to L/sub eff/=0.18 mu m, with T/sub ox/=10 nm. The p+ gate, SOI PMOS device exhibits superior I/sub dsat/ and g/sub msat/. A record propagation delay of 12 ps/stage at V/sub dd/=5 V and 300 K was obtained for the CMOS ring oscillators fabricated in this technology. This demonstrates the performance achievable with a deep-submicron SOI process.<>
  • Keywords
    BiCMOS integrated circuits; elemental semiconductors; integrated circuit technology; semiconductor-insulator boundaries; silicon; 0.18 micron; 10-mask process; 12 ps; 3.3 V; 4.5 GHz; SOI BiCMOS technology; Si; asymmetrical DDD MOSFETs; complementary lateral BJT; deep-submicron SOI process; double-diffused lateral BJTs; fully-complementary process; fully-overlapped MOSFETs; high-performance circuit operation; lateral current gain; p+ gate SOI PMOS device; propagation delay; ring oscillators; short-channel behavior; sub-3.3 V power supply regime; thin-film SOI substrates; BiCMOS integrated circuits; Integrated circuit fabrication; Semiconductor-insulator interfaces; Silicon;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Electron Devices Meeting, 1992. IEDM '92. Technical Digest., International
  • Conference_Location
    San Francisco, CA, USA
  • ISSN
    0163-1918
  • Print_ISBN
    0-7803-0817-4
  • Type

    conf

  • DOI
    10.1109/IEDM.1992.307399
  • Filename
    307399