DocumentCode
1953197
Title
Simulator-independent capacitance macro model for power DMOS transistors
Author
Pawel, S. ; Kusano, H. ; Nakamura, Y. ; Teich, W. ; Terashima, T. ; Netzel, M.
Author_Institution
TU Ilmenau, Germany
fYear
2003
fDate
14-17 April 2003
Firstpage
287
Lastpage
290
Abstract
The paper presents an easy-to-use macro model for the gate-drain and gate-source capacitances of power DMOS transistors in VLSI smart power technologies according to T. Terashima (2002). The model is a capacitance model which can be used as an add-on to any existing DC SPICE model and with any SPICE simulator and can be derived directly form measurement data.
Keywords
MOS integrated circuits; SPICE; VLSI; capacitance measurement; digital simulation; integrated circuit modelling; switching transients; DC Spice model add-on; SPICE simulator; VLSI; capacitance macro model; gate-drain capacitance; gate-source capacitances; measurement data; power DMOS transistors; simulator-independent capacitance model; smart power technologies; Capacitance measurement; Circuit simulation; Cities and towns; Driver circuits; Europe; Large scale integration; Parasitic capacitance; Power system modeling; SPICE; Voltage;
fLanguage
English
Publisher
ieee
Conference_Titel
Power Semiconductor Devices and ICs, 2003. Proceedings. ISPSD '03. 2003 IEEE 15th International Symposium on
Print_ISBN
0-7803-7876-8
Type
conf
DOI
10.1109/ISPSD.2003.1225284
Filename
1225284
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